CAN=DISABLE, ADC=DISABLE, CT16B0=DISABLE, SYS=RESERVED, RAM=DISABLE, CT16B1=DISABLE, FLASHARRAY=DISABLED, ROM=DISABLE, CT32B0=DISABLE, CT32B1=DISABLE, WDT=DISABLE, IOCON=DISABLE, FLASHREG=DISABLED, GPIO=DISABLE, SSP0=DISABLE, SSP1=DISABLE, UART=DISABLE, I2C=DISABLE
System AHB clock control
| SYS | Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. 0 (RESERVED): Reserved 1 (ENABLE): Enable |
| ROM | Enables clock for ROM. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| RAM | Enables clock for RAM. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| FLASHREG | Enables clock for flash register interface. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| FLASHARRAY | Enables clock for flash array access. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| I2C | Enables clock for I2C. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| GPIO | Enables clock for GPIO. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| CT16B0 | Enables clock for 16-bit counter/timer 0. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| CT16B1 | Enables clock for 16-bit counter/timer 1. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| CT32B0 | Enables clock for 32-bit counter/timer 0. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| CT32B1 | Enables clock for 32-bit counter/timer 1. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| SSP0 | Enables clock for SPI0. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| UART | Enables clock for UART. See Section 3.1 for part specific details. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| ADC | Enables clock for ADC. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| RESERVED | Reserved |
| WDT | Enables clock for WDT. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| IOCON | Enables clock for I/O configuration block. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| CAN | Enables clock for C_CAN. See Section 3.1 for part specific details. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| SSP1 | Enables clock for SPI1. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| RESERVED | Reserved |